1. Field of the Invention
The present invention relates to digital operational circuitry advantageously for use in a digital signal processor (DSP) and/or a large-scale integrated circuit (LSI) for processing arithmetic and logical operations and signals.
2. Description of the Background Art
In the prior art, digital signal processors which are high in processing rate and low in power consumption are required for a specific application, such as digital mobile telephone stations. Such digital signal processors are known by "DSP for Mobile Telephone by Texas Instruments, Inc., U.S. Including a Circuit for Viterbi Decoding" Nikkei Electronics, No. 602, pp. 15-16, published by Nikkei BP Corp, Tokyo, Feb. 28, 1994, for example, which teaches circuitry exclusive to waveform equalization/Viterbi decoding with a CSS (Compare Select Store) circuit involved. Another reference, Katsuhiko Ueda, et al., "A 16b Low-Power-Consumption Digital Signal Processor" Technical Report of The Institute of Electronics, Information and Communication Engineers of Japan, ICD93-92, DSP93-53, pp. 67-74, Sep. 1993, also discloses the digital signal processor achieving both high performance and low power consumption with the double-speed MAC (Multiply And Accumulation) unit and ACS (Add-Compare-Select)/Block floating accelerator.
A conventional signal processor for convolutionally encoding signals is, for example, adapted to obtain the status from the pathmetrics associated with the statuses at a discrete time point preceeding the present, discrete time point at which the earlier-mentioned status is being obtained. For facilitating the signal encoding processings to be understood, now referring to FIG. 1, there are shown in the form of Trellis diagram three discrete time points t, t+1 and t+2, at each of which eight internal statuses are established in the convolutional encoder. The exemplified convolutional encoder is implemented by the digital signal processor with its coding rate, R=1/2, constraint length, K=4, and eight statuses involved. In the figure, the legend Si(t) denotes the internal status of the encoder at the time point t, and Pi(t) the pathmetric associated with the status Si(t), where i is a null or a positive integer from unity to seven, inclusive. In addition, Bi(t+1) represents the branchmetric from discrete time points t to t+1.
For example, the pathmetric P.sub.0 (t+1) for the status S.sub.0 (t+1) is determined by the following procedure. At first, the following expressions (1) and (2) are calculated: EQU P.sub.0 (t+1)=P.sub.0 (t)+B.sub.0 (t+1) (1) EQU P.sub.0 (t+1)=P.sub.1 (t)+B.sub.1 (t+1) (2)
The likelihood of both of the pathmetrics P.sub.0 (t+1) thus obtained from the expressions (1) and (2) is then evaluated, and one which is higher in likelihood is selected as the pathmetric for the status S0(t+1). Between a couple of branchmetrics B.sub.1 (t+1) and B.sub.0 (t+1), there is established the following relation: EQU B.sub.1 (t+1)=-B.sub.0 (t+1).
Then expression (2) may be changed to EQU P.sub.0 (t+1)=P.sub.1 (t)-B.sub.0 (t+1) (2a)
In operation, the conventional digital operational circuitry proceeds the convolutional coding from the discrete time points t to t+1 in the following manner: First, at the time point t+1, the operational circuitry receives pathmetrics P.sub.0 (t) and P.sub.1 (t) together with branchmetric B.sub.0 (t+1), and calculates pathmetric P.sub.0 (t+1) on the basis of the expressions (1) and (2a) to obtain a couple of values P.sub.0 (t+1). The latter values are compared with each other in terms of likelihood to produce a bit representative of the results from the comparison. One of the two values P.sub.0 (t+1) which is higher in likelihood than the other is selected as the pathmetric for status S.sub.0 (t+1). The pathmetric P.sub.0 (t+1) thus selected is in turn stored into a storage for pathmetrics, and the results of comparison into another storage therefor. That procedure is shown in FIG. 1 as a path with the denotation of numeral "1" enclosed with a circle. In the description, the number enclosed in a circle is denoted by the corresponding number with a pair of brackets [].
The operational circuitry maintains the values of P.sub.0 (t), P.sub.1 (t) and B.sub.0 (t+1) used above to proceed to obtaining another pathmetric P.sub.4 (t+1) on the basis of the following expressions: ##EQU1##
Similarly to the process for P.sub.0 (t+1) mentioned above, two values of P.sub.4 (t+1) are obtained, and one of those values P.sub.4 (t+1) which is higher in likelihood than the other is selected as the pathmetric for status S.sub.4 (t+1). That procedure is represented in FIG. 1 by path or step [2].
As can be understood, the calculation of the pathmetric for the status S.sub.0 (t+1) immediately followed by the calculation of the pathmetric for the status S.sub.4 (t+1) in the aforementioned manner is advantageous in that the data P.sub.0 (t), P.sub.1 (t) and B.sub.0 (t+1) used for calculating the pathmetric for the status S.sub.0 (t+1) is utilized again for the purpose of calculating the pathmetric for the status S.sub.4 (t+1). In this manner, the steps [3] through [8] are executed in that order to obtain pathmetrics P.sub.1 (t+1), P.sub.5 (t+1), P.sub.2 (t+1), P.sub.6 (t+1), P.sub.3 (t+1) and P.sub.7 (t+1).
Having obtained all of the pathmetrics at the time point t+1, the operational circuitry proceeds to calculate the pathmetrics at the time point t+2 at the steps [9] through [15] shown in the figure. As may have been understood, the prior art operational circuitry, executing the steps in the orders mentioned above requires, as the statuses increase, the corresponding operational period of time for calculating the pathmetrics, resulting in delay until commencing the calculation of the pathmetrics for the statuses at the successive time points.